1. Field of the Invention
The present invention relates to a selector, line redundant method, and line redundant system which realize line switching in a switching matrix to recover from line troubles and the like and, more particularly, to a line redundant scheme which has a simple hardware arrangement and allows line switching on a port basis.
2. Description of the Prior Art
Recently, demands have arisen for an improvement in the reliability of an ATM (Asynchronous Transfer Mode) switching network with respect to line troubles. As a line redundant scheme in a case wherein ATM switching is realized on a SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy) network, an APS (Automatic Protection Switching) scheme is available, in which when a failure occurs in a Working route (Working Connection), the route is automatically switched to a protection route (Protection Connection) to continue the communication. As standards for this scheme, Bellcore (Bell Communications Research) standards, ANSI (American National Standards Institute) T1.105.01-1998, ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) G.783, and the like are defined.
There are two types of switching control schemes in APS, namely a physical layer scheme using K1/K2 bytes on a SONET framer as control information for the opposite side and an ATM layer scheme using an OAM (Operation Administration and Maintenance) cell called an APS cell as control information for the opposite side.
The physical layer scheme includes two types of schemes, namely a (1+1) scheme and (1:1) scheme. In this case, in the (1+1) scheme, on the transmission side, a data signal is copied, and the identical data signals are simultaneously sent out to the two connections, i.e., the working route and protection route. On the reception side, the data signal is normally received through the working route. When a trouble occurs on the working route, only the connection on the reception side is switched from the working route to the protection route, thereby continuing the communication of a main data signal.
In the (1:1) scheme, on the transmission side, a main data signal and sub-data signal are respectively received through the working route and protection route. On the reception side, data signals from the two routes are normally received through the respective routes. When a trouble occurs on the working route, the connection is switched from the working route to the protection route on both the sides, i.e., the transmission side and reception side, thereby continuing the communication of the main data signal.
Of the above two types of physical layer schemes, the (1+1) scheme to which the present invention is applied requires a bridge function of distributing a data signal sent to the working route on the transmission side to the protection route as well, a selector function of cutting off a data signal, of data signals input to a switch on the reception side, which is sent from the protection route, and a function of performing line switching control on a port on the opposite side by using K1/K2 bytes on a SONET frame.
For example, a conventional arrangement for a line redundant system for realizing APS is disclosed in Japanese Unexamined Patent Application Publication (KOKAI) No. 9-275405. In an embodiment in this reference, the arrangement of a dual redundant system in an ATM switch is described. A selector (input cutoff circuit) and bridge (output-side distribution circuit) exist on a common switching fabric.
The operation of this conventional system will be described below with reference to FIGS. 1, 2, and 3.
FIG. 1 shows an example of the overall arrangement of the system in a case wherein terminals 1 and 4 communicate with each other. The terminals 1 and 4 communicate with each other through ATM switching matrixes 2 and 3. Dual transmission paths are set between the ATM switching matrixes 2 and 3 by APS based on the (1+1) scheme. Dotted lines 16 indicate the flows of data signals sent out from the terminal 1 to the terminal 4. Note that in FIG. 1, an illustration of the flows of data signals from the terminal 4 to the terminal 1 is omitted.
FIG. 2 shows the detailed arrangements of a common switching fabric 13a, 0-system line accommodating section 30a-0, and 1-system line accommodating section 40a-1 of the ATM switching matrix 2 shown in FIG. 1. Note that FIG. 2 also shows the arrangement of a portion which receives data signals to be sent from the terminal 4 to the terminal 1.
FIG. 3 is a block diagram showing the detailed arrangement of the ATM switching matrix 3 in APS operation. In this case, the internal arrangement of the ATM switching matrix 3 is the same as that of the ATM switching matrix 2, and the letter added to the end of the reference numeral of each component is changed from a to b. The 0/1-system line accommodating sections 30a-0 and 40a-1 of the ATM switching matrix 2 are respectively connected to 0/1-system line accommodating sections 30b-0 and 40b-1 of the ATM switching matrix 3. A selector 19b in FIG. 3 exhibits a state after APS operation; the selector 19b selects an output from the 1-system line accommodating section 40b-1 and cuts off an output from the 0-system line accommodating section 30b-0.
As is obvious from FIGS. 1 and 2, the data signal transmitted from the terminal 1 is input to the ATM switching matrix 2 through a line accommodating section 12a and bridged (distributed) to the 0-system line accommodating section 30a-0 and 1-system line accommodating section 40a-1 by the common switching fabric 13a. The resultant signals are then output to a working route 14 and protection route 15, respectively.
As is obvious from FIGS. 1 and 3, the data signal input from the working route 14 to the ATM switching matrix 3 arrives at the terminal 4 through the 0-system line accommodating section 30b-0, a common switching fabric 13b, and a line accommodating section 12b. On the other hand, the data signal input from the protection route 15 to the ATM switching matrix 3 is input to the common switching fabric 13b through the 1-system line accommodating section 40b-1, but the output to the line accommodating section 12b is cut off by the selector (19b in FIG. 3) in the common switching fabric 13b. 
The detailed arrangement of a conventional APS scheme will be described with reference to FIG. 2. Assume that a general technique is used as a switching control function using K1/K2 bytes. A description about the detection of a trouble in the working route and the exchange of control information with opposite ports by using K1/K2 bytes after the detection will therefore be omitted.
Referring to FIG. 2, the ATM switching matrix 2 is constituted by the common switching fabric 13a, the 0-system line accommodating section 30a-0, the 1-system line accommodating section 40a-1, and an OS (Operating System) 50a. The line accommodating sections are comprised of transmission/input interfaces (to be referred to as line IFs hereinafter) 32a and 33a (0-system side) and 42a and 43a (1-system side), output ports 34a-1 to 34a-N (0-system side) and 44a-1 to 44a-N (1-system side) for accommodating a plurality of lines (N lines for each line IF in FIG. 2), input ports 35a-1 to 35a-N (0-system side) and 45a-1 to 45a-N (1-system side), and line control sections 31a and 41a which perform APS control, together with the OS 50a, by using opposite ports and K1/K2 bytes of SONET frames in APS operation.
The output ports 34a-1 to 34a-N and 44a-1 to 44a-N and input ports 35a-1 to 35a-N and 45a-1 to 45a-N are constituted by an optical module (not shown), a framer (not shown) for interfacing between a physical layer and an ATM layer, and the like. The respective pairs of 0/1-system transmission/input ports in the 0-system line accommodating section 30a-0 and 1-system line accommodating section 40a-1 are connected to switch IFs 17a-1 to 17a-n to realize a redundant arrangement.
For example, referring to FIG. 2, each of the pairs of output ports (34a-1 and 44a-1), . . . , (34a-N and 44a-N) and of input ports (35a-1 and 45a-1), . . . , (35a-N and 45a-N) has an APS redundant arrangement.
The common switching fabric 13a is comprised of a switch core 16a, switch IFs 17a-1 to 17a-n, and switch control section 80a. The switch core 16a has 2n interfaces on the transmission/reception side for the switch IFs 17a-1 to 17a-n and switches ATM cells from the respective switch IFs. The switch IFs 17a-1 to 17a-n connect the interfaces of the common switching fabric 13a to the 0/1-system line accommodating sections in pairs. The switch control section 80a controls the dual redundant arrangement in cooperation with the OS 50a. 
A bridge 18a and selector 19a are accommodated in the switch IFs 17a-1 to 17a-n. The bridge 18a has a function of simultaneously distributing a data signal from the switch core 16a to the 0-system line accommodating section 30a-0 to the 1-system line accommodating section 40a-1. The selector 19a has a cutoff function of inhibiting an unselected data signal from being input to the switch core 16a by selecting one of the 0/1-system line accommodating section pair 30a-0 and 40a-1.
As is obvious from the detailed arrangement of the ATM switching matrix 3 in FIG. 3, the following problems arise when a plurality of output ports 34b-1 to 34b-N and 44b-1 to 44b-N and input ports 35b-1 to 35b-N and 45b-1 to 45b-N are accommodated on the plurality of line accommodating sections 30b-0 and 40b-1 a predetermined number of ports at a time, and a selector 19b (input cutoff circuit) exists in the switch IF 17b-1 in the common switching fabric 13b. 
Even when only switching from the input port 35b-1 in the 0-system line accommodating section 30b-0 on the working route to the input port 45b-1 in the 1-system line accommodating section 40b-1 on the protection route is to be performed, since the selector 19b exists in the common switching fabric 13b, switching cannot be done on a input port basis. Hence, switching is done on a line accommodating section basis. As a consequence, the remaining input ports 35b-2 (not shown) to 35b-N in normal operation in the 0-system line accommodating section 30b-0 are also switched to the input orts 45b-2 (not shown) to 45b-N in the 1-system line accommodating section 40b-1. When such switching occurs, cell loss may occur in the input ports 35b-2 (not shown) to 35b-N which are normally operated.
In addition, since switching from the working route to the protection route is performed by the selector 19b, selectors 19b must be provided for all the switch IFs 17b-1 to 17b-nin the common switching fabric 13b. Consequently, the internal hardware arrangement of the common switching fabric 13b is complicated.